1. Technical Field
The present application relates generally to an improved data processing system and method. More specifically, the present application is directed to mechanisms for communication between host systems using a queuing system and shared memories.
2. Description of Related Art
Most modern computing devices make use of input/output (I/O) adapters and buses that utilize some version or implementation of the Peripheral Component Interconnect standard, which was originally created by Intel in the 1990s. The Peripheral Component Interconnect (PCI) standard specifies a computer bus for attaching peripheral devices to a computer motherboard. PCI Express, or PCIe, is an implementation of the PCI computer bus that uses existing PCI programming concepts, but bases the computer bus on a completely different and much faster serial physical-layer communications protocol. The physical layer consists, not of a bi-directional bus which can be shared among a plurality of devices, but of single uni-directional links, which are connected to exactly two devices.
FIG. 1 is an exemplary diagram illustrating a PCI Express (PCIe) fabric topology in accordance with the PCIe specification. As shown in FIG. 1, the PCIe fabric topology 100 is comprised of a host processor (CPU) 110 and memory 120 coupled to a root complex 130, which is in turn coupled to one or more of a PCIe endpoint 140 (the term “endpoint” is used in the PCIe specification to refer to PCIe enabled I/O adapters), a PCI express to PCI bridge 150, and one or more interconnect switches 160. The root complex 130 denotes the root of an I/O hierarchy that connects the CPU/memory to the I/O adapters. The root complex 130 includes a host bridge, zero or more root complex integrated endpoints, zero or more root complex event collectors, and one or more root ports. Each root port supports a separate I/O hierarchy. The I/O hierarchies may be comprised of a root complex 130, zero or more interconnect switches 160 and/or bridges 150 (which comprise a switch or PCIe fabric), and one or more endpoints, such as endpoints 170 and 182-188. For more information regarding PCI and PCIe, reference is made to the PCI and PCIe specifications available from the peripheral component interconnect special interest group (PCI-SiG) website at www.pcisig.com.
Today, PCI and PCIe I/O adapters, buses, and the like, are integrated into almost every computing device's motherboard, including blades of a blade server. A blade server is essentially a housing for a number of individual minimally-packaged computer motherboard “blades”, each including one or more processors, computer memory, computer storage, and computer network connections, but sharing the common power supply and air-cooling resources of the chassis. Blade servers are ideal for specific uses, such as web hosting and cluster computing.
As mentioned above, the PCI and PCIe I/O adapters are typically integrated into the blades themselves. As a result, the I/O adapters cannot be shared across blades in the same blade server. Moreover, the integration of the I/O adapters limits the scalability of the link rates. That is, the link rates may not scale with processor performance over time. As of yet, no mechanism has been devised to allow PCI and PCIe I/O adapters to be shared by multiple system images across multiple blades. Moreover, no mechanism has been devised to allow the PCI and PCIe I/O adapters to be provided in a non-integrated manner for use by a plurality of blades in a blade server.